When a board fails EMC testing, an ADC shows spurs nobody can explain, or an MCU resets when a relay clicks, the root cause is very often the same: decoupling done casually. The fix rarely needs exotic parts — it needs the right values, the right geometry, and a few rules applied without exception.
What Decoupling Actually Does
A decoupling capacitor is a local energy reservoir and a high-frequency shunt. When an IC switches, its current demand changes in nanoseconds; the power supply cannot deliver that step through inductance of cables, planes, and regulators. The capacitor supplies the fast transient and shorts the resulting high-frequency noise to ground. Its effectiveness is decided mostly by the inductance in series with it — not by the capacitance value printed on the body.
Choosing Values: Think Impedance, Not Folklore
The "one 100 nF per pin plus one 10 µF bulk" folklore is a starting point, not an answer. The engineering approach is the target impedance method:
- Estimate the worst transient current step ΔI and the allowed supply ripple ΔV.
- Target impedance Z = ΔV / ΔI (e.g., 3 % of 3.3 V with a 1 A step → ~0.1 Ω).
- Build a capacitor network whose impedance stays below the target from DC to the IC's highest meaningful switching frequency.
In practice that resolves to a small set: 10–47 µF ceramic (X5R/X7R) for bulk near the IC, 100 nF–1 µF per power pin group, and sometimes a smaller 10 nF for very fast edges. Watch dielectric derating: an "10 µF" 0805 X5R at 6.3 V may deliver barely 4 µF at rated bias. Check the DC-bias curves from the manufacturer, not the nominal value.
Placement: Inductance Is Geometry
Loop inductance is what kills decoupling at high frequency. Minimize it with physical layout:
- Capacitor close to the pin, on the same layer if possible. Every millimeter of trace adds ~1 nH per mm.
- Via strategy matters more than value. Via-in-pad or two vias per terminal, placed as close as fabrication allows. A capacitor 2 mm from the pin with fat vias beats the same value 8 mm away with thin ones.
- Current path thinking: power plane → via → capacitor → via → ground plane should form the smallest possible loop area. Avoid long skinny power thrones ("doghouses") around ICs.
- Group by rail. Each supply pin needs its own local network; sharing one capacitor between two pins couples noise between them.
Plane Resonances and the Big Picture
On multilayer boards the power-ground plane pair itself is a resonant cavity. Spreading many small capacitors across the board damps these resonances better than clustering everything at the regulator. For high-current devices (FPGAs, SoCs), consider many 100 nF–1 µF capacitors distributed under or around the package rather than a few large ones.
The Mistakes We See Most Often
- Capacitors connected through long thin traces to save via cost.
- High-K dielectrics (Y5V/Z5U) chosen for nominal value, then starved by DC bias.
- No bulk reservoir at the regulator output, so the regulator's control loop responds to every load step.
- Decoupling added on the schematic but routed as an afterthought in layout review week.
Getting decoupling right costs cents and layout discipline; getting it wrong costs an EMC retest. JTDZ Tech supplies MLCCs and bulk capacitors in all major sizes with real datasheets and traceable date codes — ask us for a BOM quote and we will flag bias-derating risks before you order.
