Application Solutions

Motor Drive Design Essentials: MOSFET Selection, Gate Driving, and Layout

A motor drive fails in characteristic ways: the MOSFETs survive the bench and die in the field, the current sense reads fine until the PWM speeds up, or the bridge self-destructs the day someone raises the switching frequency. All three trace back to the same disciplines — device selection, gate drive, and layout. Here is how to get them right for BLDC and DC drives.

MOSFET Selection: Two Numbers Fight Each Other

Conduction loss wants low RDS(on); switching loss wants low gate charge (Qg) and output charge. For drives switching above ~20 kHz, the product RDS(on) × Qg is the true quality metric, and the optimum sits at mid-range values of both. Beyond the headline:

  • Voltage rating: pick 1.5–2× the bus — 40–60 V devices for 12–24 V drives, 100 V class for 48 V systems — and check avalanche energy, since motor windings are inductive and mis-commutation events are real.
  • Current rating is thermal, not electrical. Datasheet "110 A" assumes an infinite heatsink; size by conduction + switching loss against your real thermal resistance.
  • Body diode and Qrr matter in bridge legs — reverse-recovery charge of the freewheeling device drives shoot-through risk and switching loss, especially at 48 V and above.

Gate Drive: The Part Most Designs Underestimate

The MOSFET switches as fast as its gate is driven, and only as safely as the driver allows:

  • Drive strength is a tuning knob. Gate resistors trade switching loss (lower R) against EMI and ringing (higher R). Split resistors (separate turn-on/turn-off paths) let you tune each edge.
  • Bootstrap supplies for high-side N-channel devices need refresh at every switching cycle — verify they survive 100 % duty commands, or add a charge pump for the top switch.
  • Dead time prevents shoot-through. Too short and both devices conduct; too long and the body diode conducts, heating the bridge and distorting commutation. Adaptive dead-time drivers pay for themselves at higher PWM frequencies.
  • dv/dt immunity: a fast-switching leg couples charge into the neighbouring gate through Cgd — Miller clamp features exist for exactly this.

Current Sensing: Pick Your Compromise

  • Low-side shunt: cheapest and easiest to amplify, but only measures one leg and ground disturbances affect it.
  • In-line shunt + isolated/high-voltage amplifier: per-phase fidelity for FOC, at the cost of a precision amp and careful Kelvin routing.
  • Magnetic (integrated or hall-based): inherent isolation and no insertion loss; check bandwidth, offset drift, and response time against your control loop.

Layout: Where Fast Edges Live or Die

  • Minimize the power loop (bus caps → high side → low side → shunt → back to caps) — every nH rings the switch node.
  • Keep gate loops tight and return them directly to the driver ground; cross-talk between phases' gate traces causes phantom turn-on.
  • Star the power grounds into a single point under the shunt; keep the controller's analog ground quiet and separate until one deliberate join.
  • Snubbers and TVS across the bus absorb what layout cannot eliminate — leave footprints for them in the first revision.

JTDZ Tech supplies power MOSFETs, gate drivers, current-sense amplifiers, and integrated three-phase modules for drive designs from 12 V to 800 V — with datasheets, date codes, and second-source options. Send us your bus voltage and motor specs and we will quote a matched power stage.

Battery-Powered System Design: Charging Topologies, Fuel Gauging, and Power Path
Choosing an ADC: Resolution, Sampling Rate, and the Analog Front End That Feeds It