Every high-performance system runs on distributed clocks, and every distributed clock traces back to a phase-locked loop. The PLL is where reference quality meets multiplication noise — and where a design that "works on paper" loses 2 ENOB in the ADC or closes the SERDES eye. Here is how the pieces interact and how to budget them.
What the Loop Actually Does
A PLL compares a divided version of its output (VCO) against a reference and steers the VCO until the phase error is zero — multiplication by N. The loop bandwidth is the design's main tuning knob, and it cuts both ways:
- Inside the loop bandwidth: the output follows the reference (and the PFD's own noise). A noisy reference passes through multiplied.
- Outside the loop bandwidth: the output follows the VCO's free-running noise. A noisy VCO dominates there.
- The optimum loop bandwidth sits where the two curves cross — widen it to clean up a bad VCO, narrow it to reject a bad reference. Most "mysterious jitter" is a loop bandwidth set without looking at both noise sources.
Phase Noise to Jitter: The Conversion That Matters
Datasheets quote phase noise in dBc/Hz across offset frequencies; systems care about rms jitter — the integral of phase noise over a specified band:
- ADC clock jitter limits SNR: SNR = −20·log10(2π × f_in × jitter). At a 100 MHz input, 1 ps of jitter caps SNR near 64 dB — regardless of the converter's resolution. This single equation decides most clock requirements.
- Integration bands matter: 12 kHz–20 MHz (SONET tradition), 1 kHz–10 MHz, or 100 Hz–100 MHz tell different stories. Always convert within the band your receiver or converter specifies — comparing jitters integrated over different bands is a common specification trap.
- Spurs count as jitter too: fractional-N spurs and reference spurs integrate into the budget; a spur inside the band can dominate an otherwise excellent phase-noise curve.
Loop Filter Design: Where Theory Meets a Real Capacitor
- A second-order passive filter (R, C, C) usually suffices; its poles set damping and bandwidth. Keep loop dynamics well-damped (phase margin 50–70°) — an underdamped loop rings on every reference disturbance and multiplies jitter near the bandwidth corner.
- Charge pump and loop filter layout are the analog discipline of the PLL: the CP output is a sensitive node; leakage or coupling there appears directly as spurs and deterministic jitter.
- Verify VCO control range and power supply pushing: a VCO that is pushed by its own supply rail turns switching noise into phase modulation — clean the PLL supply or add an LDO stage.
Multiplication, Fractional-N, and Spurs
| Architecture | Strength | Watch For |
|---|---|---|
| Integer-N | Cleanest spectrum, no fractional spurs | Channel spacing limits (PFD frequency = spacing) |
| Fractional-N | Fine resolution with high PFD frequency | Fractional spurs require dither/DSM — check spur placement |
| DDS-assisted / multiplier chains | Fine step, fast hop | DAC/DDS noise floor and alias planning |
For clock-tree distribution, remember that every buffer and fan-out adds jitter: budget the distribution network separately, prefer low-additive-noise buffers for critical branches, and keep return paths for each clock pair continuous — timing edges degrade exactly where the return path detours.
Building the Jitter Budget
- Start from the consumer: ADC aperture jitter or SERDES TX/RX clocking budget, in the band the datasheet specifies.
- Characterize the reference (or pick from vendor phase-noise plots), the PLL (noise figure and spur data), and each buffer's additive jitter.
- Sum in RSS with correlation checks — a shared reference means correlated terms that add linearly, not in quadrature.
- Leave margin for supply aging, temperature, and the measurement uncertainty of your own bench.
- Verify on the bench with a phase-noise analyzer or real-time scope of adequate noise floor — a scope measuring its own jitter tells you nothing.
JTDZ Tech supplies PLL synthesizers, jitter cleaners, clock buffers, and low-noise references from TI, Renesas, SiTime, and ADI — with phase-noise plots ready for your budget. Send us your clock requirement and integration band and we will quote the timing chain that closes it.
