Power-up is the most dangerous moment in an embedded system's life. Memories are indeterminate, I/O states float, and logic blocks wake at different times. Supervisors and reset ICs are the traffic police of power-up — cheap parts that prevent expensive field failures.
The Reset Threshold: Accuracy Matters More Than the Value
A supervisor asserting reset below 3.0 V sounds fine until your MCU's minimum operating voltage is 2.97 V and the supervisor's threshold tolerance is ±2.5 % — now reset can release while the core is still below spec. The rules:
- Threshold accuracy (±1 % or better) is what you are paying for; the nominal value is the easy part.
- Hysteresis (typically 1–5 %) prevents reset chatter when the supply hovers near threshold — critical with slowly rising or noisy rails.
- Supervise the rail that kills you. For 3.3 V systems, monitor the 3.3 V rail — and check the MCU datasheet for its actual minimum operating voltage, not its marketing voltage.
Reset Timeout: Give the Clock Time to Start
The reset pulse must outlast everything that needs to stabilize: oscillator startup (crystals can take 10–100 ms), internal regulator ramp, and boot firmware init. Fixed-timeout supervisors (typically 200 ms) cover most cases; adjustable timers exist for FPGAs that load configuration from flash. Undershooting the timeout produces the classic field symptom: works when power is applied cleanly, hangs on fast brown-out recoveries.
Watchdogs: The Second Line of Defense
- Window watchdogs beat simple watchdogs: they flag both stuck code and code that loops too fast (a runaway feeding the dog in an ISR).
- Supervisor + watchdog combos integrate both functions in one IC and typically assert reset on timeout — keep the watchdog timeout 10–100× your longest legitimate loop.
Multi-Rail Systems: Sequencing and Power-Good
FPGAs, SoCs, and mixed-signal devices with multiple supplies (core, I/O, analog) document strict requirements: which rail must rise first, and by how much. Violations cause latch-up, I/O damage, or mysterious boot failures:
| Approach | Mechanism | Fits |
|---|---|---|
| Sequencing controller | Enables rails in order, monitors power-good | FPGAs/SoCs with strict rail order |
| Voltage tracking | Slave rail follows master ratio | Core/I/O pairs needing simultaneous rise |
| Discrete PGOOD chain | Each regulator's PGOOD gates the next enable | Simple 2–3 rail systems, cost-sensitive |
PMICs integrate sequencing, monitoring, and watchdogs for processor-class systems — compare their cost against 3–4 discrete supervisors and the PCB area they replace.
Brown-Out and Field Reality
Sagging grid power, contact bounce, and battery end-of-life all produce brown-outs — supplies that dip below operating range but above reset threshold, or oscillate. Test your system by slowly ramping and cycling the supply on the bench; a design that only handles clean power-on will fail exactly where customers live. Longer reset pulses and more hysteresis are the usual fixes.
JTDZ Tech supplies supervisors, watchdog timers, sequencing controllers, and PMICs from TI, ADI, onsemi, and Renesas. Share your rail list and sequencing requirements and we will quote the monitoring parts that make power-up boring — the way it should be.
