MSP430FR6972IPMR

Description

This series of ultra-low-power MSP430FRxx FRAM microcontrollers comes in a variety of options, each featuring embedded non-volatile FRAM, a 16-bit CPU, and different sets of peripherals to meet various application needs. This architecture, combined with FRAM and peripherals across 7 low-power modes, is optimized to extend battery life in portable wireless sensing applications. FRAM is a brand-new non-volatile memory that perfectly combines the speed, flexibility, and durability of SRAM with the stability and reliability of flash memory, all while consuming less power.

Features

• Embedded Microcontroller
• 16-bit RISC architecture with up to 16MHz clock frequency
• Wide power supply range from 3.6V to 1.8V (minimum voltage limited by SVS level, see SVS specifications)

• Optimized ultra-low power modes
• Active mode: approximately 100µA/MHz
• Standby (LPM3 with low-power low-frequency internal clock source (VLO)): 0.4µA (typical)
• Real-Time Clock (RTC) (LPM3.5): 0.35µA (typical)
• Shutdown current (LPM4.5): 0.04µA (typical)

• Ultra-low power Ferroelectric RAM (FRAM)
• Nonvolatile memory up to 64KB
• Ultra-low power writes
• Fast write: 125ns per word (64KB written in 4ms)
• Unified standard memory = program, data, and storage in a single space
• 1015 write cycle endurance
• Radiation-resistant and non-magnetic

• Intelligent digital peripherals
• 32-bit hardware multiplier (MPY)
• Three-channel internal Direct Memory Access (DMA)
• RTC with calendar and alarm functions
• Five 16-bit timers each with up to seven capture/compare registers
• 16-bit and 32-bit cyclic redundancy check units (CRC16, CRC32)

• High-performance analog
• Up to 8-channel analog comparators
• 12-bit ADC with internal reference and sample-and-hold, up to 8 external input channels
• Integrated 116-segment LCD driver with contrast control

• Code security and encryption
• 128-bit or 256-bit AES security encryption/decryption coprocessor (only for MSP430FR69xx)
• True random seed for random number generation algorithms
• Lockable memory segments for IP protection and secure storage

• Versatile I/O ports
• All I/O pins support capacitive touch without external components
• Bit, byte, and word-level access (paired access supported)
• Can wake from LPM via P1–P4 ports, edge-selectable
• Programmable pull-up and pull-down on all ports

• Enhanced serial communication
• eUSCI_A0 and eUSCI_A1 support:
• UART with automatic baud rate detection
• IrDA encoding and decoding
• SPI with rates up to 10Mbps

• eUSCI_B0 and eUSCI_B1 support:
• I2C with multi-slave addressing
• SPI with rates up to 10Mbps

• Flexible clock system
• Equipped