Digital Power Control: Implementing PFC and LLC Loops on 32-bit MCUs

Digital control of switch-mode power stages used to be a luxury reserved for server PSUs. Today, a mid-range Cortex-M4 runs PFC and LLC loops with cycle-by-cycle attention to spare — and the payoff (adaptive profiles, telemetry, tunable protection) has pulled digital power into chargers, LED drivers, and industrial supplies. But the migration succeeds only when you respect what the analog controller was doing implicitly.

What the loops actually demand

• PFC (boost, average-current-mode): the inner current loop shapes the inductor current to follow the rectified line. Loop bandwidth of 5–15 kHz is typical; sampling must resolve the switching ripple — 1× per switching cycle minimum, synchronized to PWM. At 65–140 kHz switching, that is an ADC trigger every 7–15 µs with deterministic latency.
• LLC (resonant half-bridge): control is frequency modulation of a resonant tank. The loop is slower (1–5 kHz), but dead-time and burst-mode behavior around light load demand precise PWM resolution and clean mode transitions to avoid audible noise.

The Artery（雅特力科技） AT32F4 series hits this class comfortably: ADCs capable of multi-channel synchronized sampling (line voltage, inductor current, output), advanced timers with complementary PWM, dead-time insertion, and cycle-by-cycle current limiting in hardware. The hardware current-limit path matters — never route fast protection through firmware; if the ADC-to-interrupt-to-decision path is 3 µs and your FET survives 1 µs of overcurrent, firmware protection is decorative.

The firmware architecture that survives certification

• Split the timing domains. Fast loop (PFC current shaping, LLC frequency trim) runs from an ADC-interrupt or timer-triggered path with fixed worst-case latency. Slow housekeeping (telemetry, temperature derating, protocol handling) runs cooperatively at 1 ms+.
• Fixed-point or float? M4 with FPU makes float viable, but be rigorous about cycle counts at the fast-loop rate — 140 kHz gives ~1,700 cycles at 240 MHz for everything, including ADC ISR overhead.
• Anti-windup and mode blending everywhere. Light-load burst, startup soft-start, and brownout recovery are where digital controllers misbehave; each mode needs its own integrator clamps and output ranges, tested by riding the boundaries on a bench supply.

Divide the work with the power ICs

Digital control does not mean everything lives in firmware. The practical architectures pair the MCU with dedicated silicon: ETA（钰泰半导体） power management ICs handle housekeeping rails, standby, and auxiliary conversion with proven analog behavior, while the MCU owns the main loops. This split keeps the always-on domains (standby IQ, protection latching) out of the firmware's blast radius — a firmware crash must not take down the safety functions, and vice versa. ETA's controller and LDO families anchor those domains in appliance-grade designs.

Validation: what analog controllers got you for free

• Line transients. Scope captures at 0/45/90° phase of the input cycle — digital loops that sample asynchronously produce phase-dependent recovery behavior analog chips never showed.
• Light-load acoustics and efficiency. Burst-mode thresholds in firmware become tunable features — and tunable bugs. Characterize at 10%, 1%, and 0.1% load.
• Fault injection. Pull ADC lines, saturate current sensors, stall the fan derating loop — digital power must fail into a safe, documented state, not a firmware hang.

Teams migrating from analog PFC/LLC controllers should budget their first design for more bench time than BOM savings — then enjoy the compounding returns: firmware-tuned efficiency curves, field-updatable behavior, and telemetry that turns power supplies into serviceable products rather than black boxes.