An FPGA is not a faster microcontroller — it is a different computational model. Choosing one for the wrong reasons (or rejecting one for the wrong reasons) is expensive either way. Here is how to size a device honestly, compare the families, and decide whether your problem is even an FPGA problem.
When an FPGA Genuinely Wins
- True parallelism: dozens of independent timing-critical tasks (motor commutation, sensor fusion, protocol conversion) that a CPU would serialize — an FPGA executes them simultaneously in fabric.
- Deterministic latency: cycle-accurate, sub-microsecond responses with no interrupt jitter, cache misses, or OS scheduling in the path.
- Custom datapaths: signal processing at rates where a CPU's ALU is the bottleneck — filtering, FFTs, image pipelines at hundreds of MSPS.
- Exotic interfaces: multi-gigabit serial (PCIe, JESD204, 10G+ Ethernet), custom protocols, and legacy interfaces that no MCU supports natively.
- Evolving hardware requirements: interface standards that may change during the product's life — the fabric reprograms instead of respinning the board.
When none of these apply — sequential control logic, moderate I/O, standard protocols — an MCU is cheaper, lower power, and faster to develop. Be honest at this step.
Sizing: Read the Utilization Numbers, Not the Marketing LUT Count
- LUT/FF counts: real designs reach comfortable utilization at 60–80 %. A "100k LUT" device fits roughly a 60–70k-LUT design well. Size with headroom for bugs and feature creep.
- Block RAM (BRAM): the resource designers underestimate most. Line buffers for image processing, packet buffers, FIFOs — write down your memory map first; running out of BRAM forces external memory and its timing consequences.
- DSP slices: multiply-accumulate capacity defines your filter/FFT throughput. Budget: throughput × taps, checked against clock rate — the math decides the family tier.
- I/O and banks: count pins by standard (LVDS, LVCMOS banks, DDR controllers) and check bank structure — voltage groups constrain what can share a bank, and pin planning fails late more often than logic fits late.
- Transceivers: gigabit serial links each consume a dedicated transceiver; count channels and check rate classes (3–32 Gbps+) against the family.
Family Landscape
| Vendor Family Class | Positioning | Typical Use |
|---|---|---|
| Small (Lattice iCE40/ECP5, Gowin) | Low power, low cost, small BGA | Glue logic, sensor aggregation, battery devices |
| Mid (AMD Artix/Spartan, Intel Cyclone) | General-purpose fabric, reasonable cost | Video, industrial control, communications |
| High (AMD Kintex/Virtex, Intel Arria/Stratix) | DSP-rich, transceiver-heavy | Test equipment, radar, high-speed data acquisition |
| SoC FPGA (Zynq, Agilex, PolarFire) | ARM cores + fabric on one die | Embedded systems needing both software flexibility and hardware acceleration |
SoC FPGAs deserve special attention for embedded products: the software side runs Linux/bare-metal on hard ARM cores while the fabric handles the hard real-time — often replacing the MCU+FPGA two-chip architecture entirely.
The Costs the Datasheet Hides
- Power: static power scales with family tier; dynamic power with design activity. A mid-range FPGA at full toggle can draw several watts — a decisive argument against it in battery products unless the task demands it.
- Toolchain and expertise: synthesis, timing closure, and verification take specialist skills and calendar time. Budget the learning curve into the schedule, not just the salary line.
- Configuration: SRAM FPGAs need a configuration flash and power-ramp discipline; corruption of the bitstream is a field failure mode to design against.
- Price: volume unit prices are negotiable but start far above MCUs. The break-even versus a two-chip MCU+ASIC-adjacent solution is a real analysis, not a slide.
Selection Workflow
- Write the functional requirement and check honestly whether an MCU (or MCU + ASSP) covers it.
- Resource-budget the design: LUT, BRAM, DSP, I/O banks, transceivers — before looking at price lists.
- Shortlist families by resources, power, and toolchain maturity; simulate the critical datapath early.
- Check long-term availability — FPGAs live in products for a decade; pick vendors and families with industrial/military roadmap commitments.
JTDZ Tech supplies FPGAs and SoC devices from AMD/Xilinx, Intel/Altera, and Lattice, plus the configuration memories, power rails, and clocking parts around them. Share your resource estimate and interface list and we will quote devices that fit both the logic and the budget.
