Modern boards routinely mix 1.8 V MCUs, 3.3 V sensors, and legacy 5 V peripherals. The datasheets all "work together" — until an interface works at room temperature and fails on cold mornings, or an input quietly degrades after weeks of operation. Level translation done casually is one of the most common latent defects in electronics. Here is how to do it deliberately.
First Question: Is Translation Needed at All?
Check two things on every cross-voltage connection:
- Input tolerance: many modern ICs specify "5 V tolerant" or "3.3 V tolerant" inputs even while powered at 1.8 V — check the absolute maximum ratings, not the marketing table. If the input tolerates the driver's VOH, no translation is needed in that direction.
- Threshold compatibility: a 3.3 V output driving a 5 V CMOS input often fails VIH (5 V CMOS wants ≥ 3.5 V; the 3.3 V output tops out at ~3.3 V). No damage — just logic that reads high sometimes. The failure is intermittent by nature, which is what makes it dangerous.
Why Overvoltage Damages: The Abs-Max Reality
Driving 5 V into a non-tolerant 1.8 V input forward-biases the input's ESD protection diode into the core rail. Consequences range from increased leakage and degraded reliability to latch-up — a parasitic SCR turning on and shorting the supply — and outright junction damage. Some parts survive "for a while"; the datasheet's absolute maximum column is not a suggestion.
Translation Options, from Cheapest to Most Capable
| Method | Direction | Speed | Notes |
|---|---|---|---|
| Resistor divider | One-way (down) | DC–MHz (RC-limited) | Perfect for slow one-direction signals (enable pins, status lines); watch rise time with input capacitance |
| Series resistor + tolerant input | One-way (down) | DC–fast | Only where the datasheet documents current-limited tolerance |
| Open-drain + pull-up to Vref | One-way (up or down) | kHz–MHz | I2C-native; pull-up choice sets speed vs power |
| Auto-direction translator (e.g. TXB/TXS types) | Bidirectional | ~Mbps range | No direction pin; watch pull-up conflicts and bus capacitance limits |
| Direction-controlled buffer (e.g. TXB/VLVC types) | Per-channel set | 10s–100s Mbps | Predictable; best for buses where direction is known per pin |
| Dedicated voltage translator / level shifter | Configurable | 100 Mbps–Gbps | SPI, QSPI, RGMII, and high-speed interfaces; check skew and part-to-part skew for parallel buses |
The Peripherals That Deserve Special Attention
- I2C: open-drain by design — translation can be as simple as pull-ups to each rail with a proper translator, or a single BSS138-style MOSFET stage for one-direction-dominant buses. Speed classes matter: 3.4 MHz (Hs-mode) rules out casual resistor tricks.
- SPI: each line has its own direction and speed. SCLK at tens of MHz needs a real translator, not a resistor divider whose RC with input capacitance rounds every edge. Rising-time violations look like "flaky at higher clock rates" — the classic symptom.
- UART: slow and push-pull — almost any clean method works; just mind idle polarity and the tolerability of the RX input.
- Reset and enable lines: often overlooked, always connected to the pins that matter during power-up — check them against the sequencing reality, not just the steady state.
A Practical Decision Flow
- For each crossing signal: write down driver VOH/VOL, receiver VIH/VIL, receiver abs-max input, and the signal's speed.
- If thresholds already meet and input is tolerant — route directly, document why.
- Slow, one-direction → resistor divider (calculate the RC with input capacitance).
- Bidirectional or fast → purpose-built translator; check drive strength, direction scheme, and speed class against the bus.
- Verify on the bench with the real load — rise-time degradation is invisible in block diagrams.
JTDZ Tech stocks translation ICs from TI, Nexperia, and onsemi across every speed class, plus the supporting passives. Send us your mixed-voltage net list and we will quote translators sized to each bus — not one part forced everywhere.
