SPI NOR Flash Sourcing Guide: Density, Speed Class, and Endurance for Firmware Storage

Every embedded processor boots from something, and for most of the industry that something is SPI NOR flash: random-access readable, execute-in-place capable, and reliable enough to hold firmware for twenty years. It is also a commodity where spec sheets look identical and behavior differs. This guide gives buyers and engineers a shared vocabulary.

What NOR Is Actually For

• Boot and XIP: NOR supports execute-in-place — the MCU fetches code directly from the flash over QSPI, so small systems skip external RAM copies entirely.
• Firmware and OTA storage: a common architecture keeps the running image plus one update slot, which is why density classes (8 Mb, 16 Mb, 32 Mb, 64 Mb, 128 Mb+) map directly to how ambitious your OTA strategy can be.
• Configuration and calibration data: below 4 Mb, NOR competes with EEPROM; small serial EEPROMs (1 Kb–2 Mb, I2C or SPI, 1M+ cycle endurance in modern parts) remain the right tool for tiny parameter stores.

The Specifications That Matter

Two Families Worth Comparing

Puya P25Q series (普冉) targets the low-power end with a modern 40 nm SONOS process. The headline part is the 1.1 V ultra-low-power class (P25Q32SN is specified around 6.5 µW/Mbit read power) — aimed at battery and energy-harvesting AIoT nodes, TWS, and wearable SoCs — and Puya supplies known-good-die for SiP integration. The same "storage+" portfolio includes P24C-class EEPROMs, which simplifies sourcing when a design needs both code and parameter storage.

Boya BY25FQ series (博雅) pushes the performance end: STR at 133/166 MHz and DTR read up to 200 MHz, densities from 512 Kb to 2 Gb, and Octal read modes on high-density parts reaching 400 MB/s-class transfer rates — the regime where NOR feeds AI boot and model storage. Recent 1.8 V 512 Mb parts (BY25FQ512EL) add on-chip ECC (1-bit correction per 8 bytes) for data integrity, and block/chip erase times run roughly half of mainstream parts — a direct factory-throughput saving for OTA-heavy products. Reliability is specified at 100 K cycles, 20-year retention, −40 to +125 °C.

OTA-Oriented Selection Checklist

• Size for two images plus headroom: if your bootloader needs update capability too, add its slot. Under-provisioned flash is the most common OTA redesign trigger.
• Match speed class to the MCU's XIP controller: an Octal part cannot help a QSPI-only host; check supported modes (1/2/4/8 I/O, DTR) against your SoC's memory controller.
• Count your erase budget: firmware that logs data into the same array as code shares the 100 K-cycle endurance; spread writes or move logging to EEPROM.
• Check deep power-down and standby currents for battery designs — µA-class standby is standard, but verify it at your temperature extremes.
• Package and KGD options: SOP8/USON8/WSON8 for boards, WLCSP and known-good-die for SiP and module builds.

For current densities, speed classes, and cross-reference help across NOR suppliers, contact our team with your MCU's memory controller spec and target image size.